1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a multilayer wiring structure and a manufacturing method thereof.
2. Description of the Related Art
The high integration of a CMOS-LSI device and the miniaturization of a transistor device are progressing on a generation basis according to International Technology Roadmap for Semiconductors (ITRS). Accordingly, the miniaturization of a wiring inside a device and the multilayered wiring are progressing. At present, a wiring included inside a highest-performance IC chip is lengthened such that its total length reaches several to 10 km. Simultaneously, the wiring interval is narrowed and also the inter-wiring capacitance is increased. For this reason, particularly, a signal delay (or wiring delay) occurring in the wirings of a logic device serves as one of factors obstructing the speed-up of the processing rate of the CMOS-LSI device.
The wiring delay is determined on the basis of a product of the wiring resistance and the inter-wiring capacitance. For this reason, the reduction of wiring metal resistance and the reduction of inter-wiring capacitance are important to reduce the wiring delay. For the reduction of wiring metal resistance, there has been established a technique of using copper (Cu) of a lower specific resistance as the wiring metal in place of the conventionally used aluminum (Al). Semiconductor devices using Cu as the metal wiring are already being mass-produced. On the other hand, for the reduction of inter-wiring capacitance, there has been studied a low dielectric constant film (or low-k film) formed using a material of a lower specific dielectric constant as an inter-layer insulating film in place of the conventional used silicon oxide film (SiO2), which is already being put into practical use in part. The low dielectric constant film material uses an organic material of an allyl ether system, a fluorocarbon system, and the like. The specific dielectric constants of these materials are about 3, which are significantly lower than SiO2 (of the specific dielectric constant of 4). However, it is difficult to realize the dielectric constant reduction required for the next generation and future generations by only improving the material of the inter-layer insulating film. A method of introducing holes (porous) into these materials is being dominant and the development is progressing on a large scale to realize the further dielectric constant reduction. In general, a low dielectric constant film into which the holes are introduced is called a porous low-k film.
Patent Document 1: JP-A-2004-119969
Patent Document 2: JP-A-2002-30249
Patent Document 3: JP-A-2001-67963
In general, it is known that the low dielectric constant film including the porous low-k film has the property that the lower the specific dielectric constant is, the lower the mechanical strength is. FIG. 59 is a graph showing the relationship of a specific dielectric constant and an elastic modulus (or Young modulus) of various low dielectric constant films and SiO2 films using a chemical vapor deposition (CVD) method and a spin on deposition (SOD) method represented as a method of film-forming low dielectric constant films. The horizontal axis of the graph represents the specific dielectric constant and the vertical axis represents the elastic modulus (GPa) in a logarithm. As shown in FIG. 59, values of the specific dielectric constant and the elastic modulus of the low dielectric constant film, the SiO2 film, and the like are measurably varied, but the logarithms of the specific dielectric constant and the elastic modulus are mostly in the proportional relationship. That is, it turns out that the lower the specific dielectric constant of the insulating film is, the lower the mechanical strength is.
As LSI fabrication processes, there are a process in which a stress is generated in a direction perpendicular to a substrate surface as in a bonding process and a process in which a stress is generated in a substrate in-plane direction as in a polishing process using a chemical mechanical polishing (CMP) method. Moreover, in a dicing process for cutting an IC chip and a package state subsequent thereto, a complex stress including a shear stress is generated inside a device. In the semiconductor device using a low dielectric constant film for reducing the inter-wiring capacitance, it is difficult to secure a sufficient mechanical strength to these stresses. Therefore, there is a problem in that the reliability and the manufacturing yield are lowered since the deformation, the wiring disconnection, and the like are apt to occur in the semiconductor device using the low dielectric constant film. This problem should be addressed to realize next generation CMOS-LSI devices.
It is known that not only the mechanical strength is low, but also the thermal conductivity is low since the density of the porous low-k film is low in general. When the thermal conductivity of the insulating film arranged around the wiring is low, it is difficult to discharge the heat from the wiring outside the substrate and chip. For this reason, particularly, there is a problem in that a temperature is raised at the time of a chip operation in the semiconductor device using the porous low-k film.
Patent Document 1 discloses a technique for providing a mechanical reinforcement plug without a function of an electrical circuit. In association with this, there is disclosed a technique for providing a reinforcement wiring layer (or a reinforcement conductive layer or a sacrificial wiring). The reinforcement plug and the reinforcement wiring layer are formed using Cu or the like. Accordingly, the improvement of the mechanical strength of the entire chip and the adherence density in the interface is expected. However, in this case, a new parasitic capacitance is formed between the wiring-reinforcement plug and between the wiring-reinforcement wiring layer since the reinforcement plug and the reinforcement wiring layer are provided separately from the conventional wiring and via. That is, the performance of the semiconductor device is lowered by reinforcing the mechanical strength. Moreover, since these reinforcement portions should be arranged in advance in the design step, the design constraint is also large.